1. Technical Field
The present invention relates to a semiconductor device and to a method of manufacturing method thereof, and in particular to a WCSP semiconductor device having a multilayer redistribution structure and a manufacturing method thereof.
2. Related Art
In conventional integrated circuit packages of packaged semiconductor chips, such as semiconductor integrated circuits and the like, demands are increasing for size reduction and reduction in thickness. Recently, development is progressing in Chip Sized Packages (CSP's), centered around integrated circuit packages in fields with particular demands for reduced thickness. CSP's have spherical shaped external connection terminals, called bumps, disposed in a lattice on the surface of a semiconductor chip. A structural body that includes plural individual semiconductor devices formed on a semiconductor wafer by wafer processing, from which CSP's are obtained by dicing, is referred to as a WCSP (Wafer-level Chip Size Package).
Recently, multilayer redistribution structures are being introduced even in WCSP's, in order to obtain a higher degree of integration. In such multilayer redistribution structure WCSP's, in order to obtain an even higher degree of integration, a “stacked structure”, formed by via portions corresponding to each layer superimposed on an electrode pad, is proposed (Japanese Patent Application Laid-Open (JP-A) No. 2002-252310). So-called stacked vias exist. For example, FIG. 2 of JP-A No. 2002-252310 is a diagram of a WCSP having a structure of a first metal layer (redistribution layer) formed on a semiconductor wafer 2, with a first insulating pattern layer in between, so as to be connected to a signal electrode pad 4a, and with a second metal layer (redistribution layer) additionally formed thereon, with a second insulating layer in between.
However, there is the problem that in a conventional multilayer redistribution structure WCSP there is variation in the thickness of the redistribution layers along the wafer surface, generating variation in the electrical properties, as represented by the Quality Factor, or the like. In particular, there is significant variation in electrical properties in WCSP's of stacked structure. For example, in the structure shown in FIG. 2 of JP-A No. 2002-252310, due to the step in the vicinity of the opening of the signal electrode pad 4a portion, and the like, local variation is generated in the thickness of the first metal layer (redistribution layer) formed thereon. Furthermore, there is also variation in the thickness of the second insulating layer formed on the first metal layer, and there is also variation in the thickness of the second metal layer (redistribution layer) formed on the second insulating layer. As a result, there is variation in the thickness of the redistribution layers of the WCSP overall.
In a process where redistribution layers are grown by “electroplating”, variation in thickness of the redistribution layers has conventionally been controlled by controlling various parameters, such as the current density, electroplating flow rate, and the like. However, demands for raised electrical properties, such as Quality Factor, have recently been increasing, and a further reduction in the variation in thickness of the redistribution layers is required. It has become difficult to contain the variation within the desired range by means of conventional parameter control alone.